1. Field of the Invention
The invention relates generally to semiconductor memories. In particular, the invention relates to a charge amplifying cell built in a trench.
2. Background Art
Dynamic memory cells have become the most common type of inexpensive semiconductor memory. Their operation relies upon the selective storage of a charge on a cell node (capacitance) and the later reading of the quantity of this charge to determine the stored data value. As fabrication techniques have become increasingly sophisticated, the size of the storage cell has decreased and therefore, for the most part, the size of the stored charge has also decreased. However, it has become increasingly difficult to read the very small stored charges. During the reading operation, the stored charge is usually distributed over the bit line connecting the storage node to the sense amplifier so that the resultant voltage can become very small. Also, there is inevitably some noise present on the integrated circuit which can mask the small voltage variations produced by the stored charge.
One solution has been the charge amplifying cell, such as disclosed by Joshi et al. in U.S. Pat. No. 4,168,536. In such a cell, a charge is selectively gated onto a storage node or capacitor by a write transistor. Thereafter, the write transistor is switched off and the amount of stored charge becomes the stored data value. One of the sides of the capacitor is coupled to the gate of a read transistor. By various techniques, when it is desired to read the stored data value, a current passing through the read transistor (determined by its conductance and thus the amount of stored charge) is measured. The measurement can involve the passage of a substantial current through the read transistor. The important point is that the charge on the storage node only controls the read transistor, is not directly detected and is not directly affected by the reading current. That is, the stored charge is amplified by the reading transistor. Therefore, a relatively small storage charge on a relatively small capacitor can cause a large current to be read.
As the number of elements on a dynamic semiconductor memory chip has increased, one of the techniques used to provide a relatively large storage capacitance using a relatively small chip area has used trench technology. In this techniques, a relatively deep trench with vertical sidewalls are formed in the substrate. Then a capacitor is formed on one or more of the vertical sidewalls. Thereby, the top surface area of the chip occupied by the capacitor can be much less than the area of the capacitor itself. There are many examples of such dRAM (dynamic random access memory) trench cells, such as Mashiko et al., "A 4-Mbit DRAM with Folded-Bit-Line Adaptive Sidewall-Isolated Capacitor (FASIC) Cell", appearing in IEEE Journal of Solid-State Circuits, vol. SC-22, no. 5, October 1987, pages 643-649. Another, example is U.S. Pat. No. 4,785,337, issued November 1988, by the present inventor and entitled "Dynamic RAM Cell Having Shared Trench Storage Capacitor with Sidewall-Defined Bridge Contacts and Gate Electrodes". This last reference is incorporated herein by reference because of its full description of trench technology.
The proposals to date for charge amplifying dRAM cells have resulted in layouts which are much larger than the conventional dRAM cells or utilize an operating principle which is undeveloped or marginal.